ASIC Architecture and Design Engineer, Machine Learning Accelerator
Minimum qualifications:
- Master’s degree in Electrical Engineering, Computer Science, or a related field or equivalent practical experience.
- 1 year of experience in RTL design.
- Experience in logic synthesis, verification, timing closure and physical design principles.
- Experience in applying computer architecture principles to solve open-ended problems.
Preferred qualifications:
- PhD in Electrical Engineering or Computer Science or a related field.
- 3 years of experience in FPGA/ASIC design and ASIC development.
- Experience in computer arithmetic and analyzing power/performance/area trade-offs for ALU (arithmetic logic unit) components.
- Experience in pipeline designs and multiple-clock domain designs.
- Experience in modeling mathematical components.
- Knowledge of processor design, accelerators, and/or memory hierarchies, and machine learning algorithms.
About the job
Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
In this role, you will be a part of a team developing Application Specific Integrated Circuits (ASICs) used to accelerate computation in data centers. You’ll have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of data center accelerators.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google’s product portfolio possible. We’re proud to be our engineers’ engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Understand the overall application of the chip, proposing and developing improvements in mathematical components based on new applications or research, as well as in overall design.
- Design and document one or more blocks of an ASIC, including functionality and timing, while applying engineering best practices.
- Implement designs in RTL (System Verilog or other HDLs) and iterate the design for optimal power, timing and area.
- Create simple test benches and debug complex logic simulations.
- Work closely with compiler and software teams on functionality, interfaces, and documentation.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also and If you have a disability or special need that requires accommodation, please let us know by completing our .
